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cy7c1069dv33 16-mbit (2 m 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05478 rev. *g revised october 21, 2011 16-mbit (2 m 8) static ram features high speed ? t aa = 10 ns low active power ? i cc = 175 ma at 100 mhz low complementary metal oxide semiconductor (cmos) standby power ? i sb2 = 25 ma operating voltages of 3.3 0.3 v 2.0 v data retention automatic power-down when deselected transistor-transistor logic (ttl) compatible inputs and outputs easy memory expansion with ce 1 and ce 2 features available in pb-free 54-pin thin small outline package (tsop) type ii and 48-ball very fine-pitch ball grid array (vfbga) packages. functional description the cy7c1069dv33 is a high per formance cmos static ram organized as 2,097,152 words by 8 bits. to write to the device, take chip enables (ce 1 low and ce 2 high) and write enable (we ) input low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 20 ). to read from the device, take chip enables (ce 1 low and ce 2 high) and output enable (oe ) low while forcing the write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. see truth table on page 10 for a complete description of read and write modes. the input and output pins (i/o 0 through i/o 7 ) are placed in a high impedance state when the device is deselected (ce 1 high or ce 2 low), the outputs are disabled (oe high), or during a write operation (ce 1 low, ce 2 high, and we low). the cy7c1069dv33 is available in a 54-pin tsop ii package with center power and ground (revolutionary) pinout, and a 48-ball very fine-pitch ball grid array (vfbga) package. logic block diagram 15 16 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer 2 m x 8 array a 0 a 12 a 14 a 13 a a a 17 a 18 a 10 a 11 i/o 0 ? i/o 7 oe ce 2 we ce 1 a 9 a 19 a 20 [+] feedback
cy7c1069dv33 document number: 38-05478 rev. *g page 2 of 15 contents selection guide ................................................................ 3 pin configurations ........................................................... 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 dc electrical characteristics .......................................... 4 capacitance ...................................................................... 5 thermal resistance .......................................................... 5 ac test loads and waveforms ....................................... 5 ac switching characteristics ......................................... 6 data retention characteristics ....................................... 7 data retention waveform ................................................ 7 switching waveforms ...................................................... 7 truth table ...................................................................... 10 ordering information ...................................................... 10 ordering code definitions ..... .................................... 10 package diagrams .......................................................... 11 acronyms ........................................................................ 13 document conventions ................................................. 13 units of measure ....................................................... 13 document history page ................................................. 14 sales, solutions, and legal information ...................... 15 worldwide sales and design s upport ......... .............. 15 products .................................................................... 15 psoc solutions ......................................................... 15 [+] feedback
cy7c1069dv33 document number: 38-05478 rev. *g page 3 of 15 selection guide - 10 unit maximum access time 10 ns maximum operating current 175 ma maximum cmos standby current 25 ma pin configurations figure 1. 54-pin tsop ii (top view) [1] figure 2. 48-ball vfbga (top view) [1] 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 nc 18 17 20 19 23 28 25 24 22 21 27 26 v ss nc nc v cc nc i/o 6 v ss a 16 a 17 a 11 a 12 a 13 a 14 i/o 0 a 15 i/o 3 i/o 5 v cc i/o 4 i/o 7 a 19 a 4 a 3 a 2 a 1 ce 1 v cc we ce 2 a 20 nc v ss oe a 8 a 7 a 6 a 5 a 0 nc a 9 nc a 10 10 a 18 46 45 47 50 49 48 51 54 53 52 nc i/o 1 nc v ss v cc v ss i/o 2 nc v cc nc we a 11 a 10 a 6 a 0 a 3 ce 1 nc nc i/o 0 a 4 a 5 i/o 1 nc i/o 2 i/o 3 nc v ss a 9 a 8 oe a 7 nc nc ce 2 a 17 a 2 a 1 nc i/o 4 nc i/o 5 i/o 6 nc i/o 7 nc a 15 a 14 a 13 a 12 nc a 19 a 20 3 26 5 4 1 d e b a c f g h a 16 a 18 v cc v cc v ss note 1. nc pins are not connected on the die. [+] feedback
cy7c1069dv33 document number: 38-05478 rev. *g page 4 of 15 maximum ratings exceeding maximum ratings may shorten the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?65 ? c to +150 ? c ambient temperature with power applied .... .............. .............. .......... ?55 ? c to +125 ? c supply voltage on v cc relative to gnd [2] ................................?0.5 v to +4.6 v dc voltage applied to outputs in high z state [2] ................................ ?0.5 v to v cc + 0.5 v dc input voltage [2] ............................. ?0.5 v to v cc + 0.5 v current into outputs (low) ........................................ 20 ma static discharge voltage (mil-std-883, method 3015) ................................. > 2001 v latch-up current .................................................... > 200 ma operating range range ambient temperature v cc industrial ?40 ? c to +85 ? c 3.3 v ? 0.3 v dc electrical characteristics over the operating range parameter description test conditions - 10 unit min max v oh output high voltage min v cc , i oh = ?4.0 ma 2.4 ? v v ol output low voltage min v cc , i ol = 8.0 ma ? 0.4 v v ih input high voltage ? 2.0 v cc + 0.3 v v il input low voltage [2] ? ?0.3 0.8 v i ix input leakage current gnd < v in < v cc ?1 +1 ? a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 ? a i cc v cc operating supply current v cc = max, f = f max = 1/t rc, i out = 0 ma, cmos levels ?175ma i sb1 automatic ce power-down current ? ttl inputs max v cc , ce 1 > v ih , ce 2 < v il , v in > v ih or v in < v il , f = f max ?30ma i sb2 automatic ce power-down current ? cmos inputs max v cc , ce 1 > v cc ? 0.3 v, ce 2 < 0.3 v, v in > v cc ? 0.3 v or v in < 0.3 v, f = 0 ?25ma note 2. v il(min) = ?2.0 v and v ih(max) = v cc + 2 v for pulse durations of less than 20 ns. [+] feedback
cy7c1069dv33 document number: 38-05478 rev. *g page 5 of 15 capacitance parameter [3] description test conditions tsop ii vfbga unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 3.3 v 6 8 pf c out io capacitance 8 10 pf thermal resistance parameter [3] description test conditions tsop ii vfbga unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four layer printed circuit board 24.18 28.37 ? c/w ? jc thermal resistance (junction to case) 5.40 5.79 ? c/w ac test loads and waveforms figure 3. ac test loads and waveforms [4] 90% 10% 3.0 v gnd 90% 10% all input pulses 3.3 v output 5 pf* including jig and scope (b) r1 317 ? r2 351 ? rise time > 1 v/ns fall time: > 1 v/ns (c) output 50 ? z 0 = 50 ? v th = 1.5 v 30 pf* * capacitive load consists of all components of the test environment high z characteristics (a) notes 3. tested initially and after any design or proce ss changes that may affect these parameters. 4. valid sram operation does not occur until the power supplies have reached the minimum operating v dd (3.0 v). 100 ? s (t power ) after reaching the minimum operating v dd , normal sram operation begins including reduction in v dd to the data retention (v ccdr , 2.0 v) voltage. [+] feedback
cy7c1069dv33 document number: 38-05478 rev. *g page 6 of 15 ac switching characteristics over the operating range parameter [5] description - 10 unit min max read cycle t power v cc (typical) to the first access [6] 100 ? ? s t rc read cycle time 10 ? ns t aa address to data valid ? 10 ns t oha data hold from address change 3 ? ns t ace ce 1 low/ce 2 high to data valid ? 10 ns t doe oe low to data valid ? 5 ns t lzoe oe low to low z [7] 1?ns t hzoe oe high to high z [7] ?5ns t lzce ce 1 low/ce 2 high to low z [7] 3?ns t hzce ce 1 high/ce 2 low to high z [7] ?5ns t pu ce 1 low/ce 2 high to power-up [8] 0?ns t pd ce 1 high/ce 2 low to power-down [8] ?10ns write cycle [9, 10] t wc write cycle time 10 ? ns t sce ce 1 low/ce 2 high to write end 7 ? ns t aw address setup to write end 7 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 7?ns t sd data setup to write end 5.5 ? ns t hd data hold from write end 0 ? ns t lzwe we high to low z [7] 3?ns t hzwe we low to high z [7] ?5ns notes 5. test conditions assume signal transition time of 3 ns or less , timing reference levels of 1.5 v, and input pulse levels of 0 to 3.0 v. test conditions for the read cycle use output loading shown in (a) of figure 3 on page 5 , unless specified otherwise. 6. t power gives the minimum amount of time that the power supply is at typical v cc values until the first memory access is performed. 7. t hzoe , t hzce , t hzwe , t lzoe , t lzce , and t lzwe are specified with a load capacitance of 5 pf as in (b) of figure 3 on page 5 . transition is measured ? 200 mv from steady state voltage. 8. these parameters are guaranteed by design and are not tested. 9. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , and ce 2 = v ih . ce 1 and we are low along with ce 2 high to initiate a write, and the transition of any of these signals can terminate. the input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 10. the minimum write cycle time for write cycle no. 2 (we controlled, oe low) is the sum of t hzwe and t sd . [+] feedback
cy7c1069dv33 document number: 38-05478 rev. *g page 7 of 15 data retention characteristics over the operating range parameter description conditions min max unit v dr v cc for data retention 2 ? v i ccdr data retention current v cc = 2 v, ce 1 > v cc ? 0.2 v, ce 2 < 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v ? 25 ma t cdr [11] chip deselect to data retention time 0?ns t r [12] operation recovery time t rc ?ns data retention waveform figure 4. data retention waveform 3.0 v 3.0 v t cdr v dr > 2 v data retention mode t r ce v cc switching waveforms figure 5. read cycle no. 1 (address transition controlled) [13, 14] previous data valid data out valid rc t aa t oha t rc address data i/o notes 11. tested initially and after any design or proce ss changes that may affect these parameters. 12. full device operation requires linear v cc ramp from v dr to v cc(min) > 50 ? s or stable at v cc(min) > 50 ? s. 13. the device is continuously selected. ce 1 = v il , and ce 2 = v ih . 14. we is high for read cycle. [+] feedback
cy7c1069dv33 document number: 38-05478 rev. *g page 8 of 15 figure 6. read cycle no. 2 (oe controlled) [15, 16] switching waveforms (continued) 50% 50% data out valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t pd t hzce oe ce 1 address data i/o v cc supply current ce 2 high impedance i cc i sb notes 15. we is high for read cycle. 16. address valid before or similar to ce 1 transition low and ce 2 transition high. [+] feedback
cy7c1069dv33 document number: 38-05478 rev. *g page 9 of 15 figure 7. write cycle no. 1 (ce controlled) [17, 18, 19] figure 8. write cycle no. 2 (we controlled, oe low) [17, 18, 19] switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc data io address ce we data in valid t hd t sd t sce t ha t aw t pwe t wc t sa t lzwe t hzwe data i/o address ce we data in valid notes 17. ce is a shorthand combination of both ce 1 and ce 2 combined. it is active low. 18. data i/o is high impedance if oe = v ih . 19. if ce goes high simultaneously with we going high, the output remains in a high impedance state. [+] feedback
cy7c1069dv33 document number: 38-05478 rev. *g page 10 of 15 truth table ce 1 ce 2 oe we i/o 0 ?i/o 7 mode power h x x x high z power-down standby (i sb ) x l x x high z power-down standby (i sb ) l h l h data out read all bits active (i cc ) l h x l data in write all bits active (i cc ) l h h h high z selected, outputs disabled active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 10 cy7c1069dv33-10zsxi 51-85160 54-pin tsop ii (pb-free) industrial CY7C1069DV33-10BVXI 51-85178 48-ball vfbga (pb-free) ordering code definitions temperature range: i = industrial pb-free package type: xx = zs or bv zs = 54-pin tsop ii bv = 48-ball vfbga speed: 10 ns voltage range: v33 = 3 v to 3.6 v process technology: d = c9, 90 nm data width: 9 = 8-bits 06 = 16-mbit density 1 = fast asynchronous sram family technology code: c = cmos marketing code: 7 = sram company id: cy = cypress c cy 1 - 10 xx 7 06 d i v33 9 x [+] feedback
cy7c1069dv33 document number: 38-05478 rev. *g page 11 of 15 package diagrams figure 9. 54-pin tsop type ii (22.4 11.84 1.0 mm) z54-ii package outline, 51-85160 51-85160 *c [+] feedback
cy7c1069dv33 document number: 38-05478 rev. *g page 12 of 15 figure 10. 48-ball vfbga (8 9.5 1.0 mm) bv48b package outline, 51-85178 package diagrams (continued) 51-85178 *a [+] feedback
cy7c1069dv33 document number: 38-05478 rev. *g page 13 of 15 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory vfbga very fine-pitch ball grid array tsop thin small outline package ttl transistor-transistor logic we write enable symbol unit of measure c degree celsius mhz megahertz ? a microampere ? s microsecond ma milliampere ns nanosecond ? ohm % percent pf picofarad v volt w watt [+] feedback
cy7c1069dv33 document number: 38-05478 rev. *g page 14 of 15 document history page document title: cy7c1069dv33, 16-mbit (2 m 8) static ram document number: 38-05478 rev. ecn no. issue date orig. of change description of change ** 201560 see ecn swi advance datasheet for c9 ipp *a 233748 see ecn rkf modified ac, dc parameters as per eros (specification 01-2165) pb-free offering in the ordering information *b 469420 see ecn nxr converted from advance information to preliminary removed -8 and -12 speed bins from product offering removed commercial operating range changed 2g ball of fbga and pin 40 of tsopii from dnu to nc included the maximum ratings for static discharge voltage and latch up current on page 3 changed i cc(max) from 220 ma to 100 ma changed i sb1(max) from 70 ma to 30 ma changed i sb2(max) from 40 ma to 25 ma specified the overshoot s pecification in footnote 1 added data retention characteristics table on page 5 updated the 48-pin fbga package updated the ordering information table. *c 499604 see ecn nxr added note 1 for nc pins updated test condition for i cc in dc electrical characteristics table updated the 48-ball fbga package *d 1462585 see ecn vkn / aesa converted from preliminary to final changed i cc spec from 125 ma to 175 ma updated thermal specs *e 3109063 12/13/2010 aju added ordering code definitions . updated package diagrams . *f 3147335 01/19/2011 pras added acronyms and units of measure table. updated the datasheet as per template. *g 3417274 10/21/2011 tava updated features . updated dc electrical characteristics . updated switching waveforms . [+] feedback
document number: 38-05478 rev. *g revised october 21, 2011 page 15 of 15 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1069dv33 ? cypress semiconductor corporation, 2006-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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